PDF datasheet for the TI SN74LVT16952DGGR, a 3.3 V 16-bit registered bus transceiver from the LVT logic family. DGG denotes the TSSOP package and R indicates tape-and-reel packaging. At 38.6 KB it is a fairly short document. Use the pin table to locate the clock, clock-enable and output-enable signals for each direction when you debug latched data paths. Because data passes through internal registers, a missing clock edge rather than a failed IC may explain why values never reach the far side of the bus.
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